11 Sept 2024, Wednesday | 16:25 - 17:50 Hrs

Location: IEML, Level 2, Hall 2, Conference Room 2

Design / EDA (In collaboration with IESA)

Synopsis:

The chip design ecosystem is experiencing rapid transformation. Emerging processes, advanced assembly technologies, and novel applications are introducing new challenges in complexity, verification, power, device and supply chain security, and more. 

In this session, we will explore the march of technology in chip design and how tool vendors are evolving to equip designers with the capabilities needed to create and verify the next generation of chips.

Program Outline

TimeProgram
16:25 - 16:30Opening Remarks by Session Chair
16:30 - 16:45

Keynote: Memory at the core of the AI Momentum – Unleashing the AI Revolution through Pioneering Innovations in Memory and Storage Systems

Subhash Chintamaneni, Senior Director,ASIC Development Engineering, Micron Technology

16:45 - 17:00

3D-IC Technology: Signoff Challenges & Solutions

Arvind Veeravalli, Senior Software Architect, Cadence Design Systems​

17:00 - 17:15

Static Signoff and Hardware Security​

Ashish Hari, Country Head - India R&D, Real Intent

17:15 - 17:45

Panel Discussion: EDA Responds to the Challenges of Advanced Manufacturing Technologies

Moderator:
Nitin Dahad, Editor-in-Chief, EE Times

Panelists:
- Dave Kelf, CEO, Breker Verification System
- Roopashree HM, Global Director - EDA, Texas Instruments
- Aveek Sarkar, Vice President, Synopsys
 

17:45 - 17:50Closing Remarks by Session Chair